Thread and Data Mapping in Shared Memory Architectures

Matthias Diener, PhD, Federal University of Rio Grande do Sul (UFRGS), Porto Alegre (Brazil)

25 Feb 2016, 17:00–18:30; Location: S4|10-1

Modern parallel architectures have a complex memory hierarchy, which consists of several cache levels and multiple memory controllers per system. In such architectures, the performance of memory accesses from a thread depends highly on which core the thread is executing and on which cache/memory controller the data is located. Therefore, it is important to understand and improve the memory access behavior of parallel applications in order to achieve optimal performance results.

In this talk, we present two techniques, thread and data mapping, that optimize the assignment of threads to cores and memory pages to memory controllers, taking into account the memory access behavior of the parallel application. Together, these techniques can achieve significant performance and energy efficiency improvements compared to traditional operating system policies.

Category: CE Seminar


Technische Universität Darmstadt

Graduate School CE
Dolivostraße 15
D-64293 Darmstadt

Phone+49 6151/16-24401
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