2010-07-22

Advanced Modeling Techniques for 3D Electronic Package Signal Integrity and Power Integrity

Prof. ErPing Li, Institute of High Performance Computing A*STAR, Singapore

13 Sep 2010, 11:30; Location: S4|10-1

Driven by the impressive growth of the communication industry, we see a rapid convergence of digital computing and analog wireless technology. This has become possible due to the progress of, semiconductor technology into the nanometer regime which is going to continue for the next ten to fifteen years. High-level integration with unprecedented functionality has been achieved through 3D packaging techniques known as system-on-chip (SOC) or system-in-package (SIP) designs. Key aspects of this technology are stacked substrates to form a multilayered package which provides an additional degree of freedom in the package design on the one hand. On the other hand, vertical integration has introduced a new degree of design complexity. Traditionally, signal and power distribution networks (SDN and PDN) have been analyzed separately because they were located far away from each other on a 2D PCB. This is no longer possible since in today’s 3D packages the layers containing SDN and PDN are in close proximity. Global coupling effects such as simultaneous switching noise (SSN) demand a modeling methodology on the system level requiring co-simulation of signal and power integrity. Therefore, new modeling approaches are in high demand to solve the challenges imposed by the complexity of nano-scale silicon chips and the necessary packaging. This presentation will overview the advancements of computational electromagnetics with applications in complex 3-dimensional electronics package integration and to address the challenges in system-level signal and power integrity and electromagnetic interference analysis.

Category: CE Seminar

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Technische Universität Darmstadt

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